It is an organizer’s delight when participants of an event show up on time or even a little earlier than the stipulated time. This was the case on March 24, when a full-day tutorial on the topic of “Design Verification with Verilog and System Verilog” was held in Bangalore. The event was organized by IEEE CAS Bangalore Chapter in cooperation with IEEE Bangalore Section. Some of the participants had travelled long distances to attend the event. The audience was a mix of students, teachers from engineering colleges, and a few professionals. About 30% of the 28 participants were members of IEEE.
I started by asking the participants to introduce themselves and say a sentence about what they were excited about! It appeared that the participants were excited to learn about VLSI design, Verilog, System Verilog and industrial design practices! The tutorial was hands-on, with simulation exercises. The participants made use of public-domain tools. Starting from a simple combinational logic design, several concepts of Verilog HDL were unfolded. The basic example was refined successively to illustrate further concepts. The next exercise was about synchronous sequential logic design. Once again, we started with an example that was small and grew it to include more advanced concepts. We looked at the example of a built-in self-test system. Finally, we looked at System-Verilog, the motivation for SV, and the new language constructs that SV includes to simplify the task of a verification engineer.
There was an online test that the participants took at the end of the tutorial. The average score was 78%. The top three scorers also received prizes! The feedback for the workshop, on a scale of 5, was as follows.
|Well were the class objectives met?||4.00|
|How knowledgeable was the instructor?||4.82|
|The instructor’s explanations were clear and adequate.||4.29|
|The instructor encouraged and was open to participation.||4.47|
|What is your overall impression of the class?||4.29|
There were several qualitative comments:
|Highly enjoyed this workshop. Got an insight into industrial practices that take place in the semiconductor industry. Obtained a lot more than what I expected from this program.|
|This hands-on workshop was very interactive and well conducted. The explanation was really good and helped us a lot when it comes to the topic of Verilog.|
|Would like to participate in similar workshops in days to come.|
|I am able to know much more System Verilog.|
|It would have been useful if they concentrated more on System Verilog.|
|Try to conduct a min 3-day event. One day is not sufficient. Conduct some program exclusively for research scholars.|
I enjoyed conducting the workshop, since the participants were enthusiastic and eager to learn. My thanks to IEEE Bangalore Section for their support. In particular, I thank Suraj for his help in publicizing the event and to Divya M for attending the valedictory program and talking to the participants about the benefits of IEEE membership.