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Hands-on Introduction to Design and Verification through Verilog and System Verilog

 

Organized by: IEEE CAS Bangalore Chapter and Supported by: Texas Instruments, India and IEEE Bangalore Section
Speaker: Dr. C.P. Ravikumar (Texas Instruments India)
Date: 24 March 2018 (Saturday)
Time: 9.00 AM to 5.00 PM
Venue: Texas Instruments India, Bangalore Campus, Bagmane Techpark, CV Raman Nagar

 

In this one-day program targeted at students and faculty, the participants will get an introduction to the topic of digital design verification. In particular, we will discuss Verilog and System Verilog and provide examples of RTL coding and development of testbenches. The student must have taken a class on Digital Design and must be familiar with combinational and sequential logic design. Prior exposure to VLSI Design and VHDL or Verilog will be useful. PCs will be available to participants for carrying out hands-on exercises.

Registration: Participants must register online by March 10, and make the payment either through NEFT or by sending a cheque/DD to reach us by March 13, 2018. Registration will be confirmed with further details.

For more details on the program and registration:

http://ieee-cas-bangalore.org/activities/events/verilog-mar18.html

 

Registration link:

https://docs.google.com/forms/d/e/1FAIpQLSdI5fM6QIye2Y9Sh9o5AY8UtVjRif5xnDZ7pazFSlm9686GEQ/viewform?usp=sf_link

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